1. Field of the Invention
The present invention relates to methods for filling containers, trenches, or other recesses of semiconductor device structures during fabrication thereof. Particularly, the present invention relates to the use of spin coating techniques to fill containers, trenches, and other recesses of semiconductor device structures. As a specific example, the present invention relates to a method for masking hemispherical grain (HSG) silicon-lined containers of a stacked capacitor structure to facilitate removal of HSG silicon from the surface of a semiconductor device structure including the stacked capacitor structure.
2. Background of Related Art
Conventionally, spin-on processes have been used to apply substantially planar layers of material to the surfaces of semiconductor device structures being fabricated upon a wafer of semiconductor material (e.g., a silicon, gallium arsenide, or indium phosphide wafer) or other semiconductor substrate (e.g., a silicon on insulator (SOI), silicon on glass (SOG), silicon on ceramic (SOC), silicon on sapphire (SOS), or other similar substrate). Consequently, while the portions of a spun-on layer of material over substantially horizontal structures may be substantially planar, the layer of material may not substantially fill or conform to the numerous, minute recesses formed in the semiconductor device structure.
For example, when it is desirable to mask a container, trench, or other recess of a semiconductor device structure without masking the surface of the semiconductor device structure to which the container, trench, or other recess opens, a mask material is typically applied to the surface of the semiconductor device structure, such as by use of known spin-on processes. As an example, FIG. 1 illustrates the fabrication of a stacked capacitor structure 10 with conductively doped HSG silicon 16-lined containers 14. As it is necessary to remove HSG silicon 16 from a surface 12 of an electrical insulator layer 11 (e.g., borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), or borosilicate glass (BSG)) of stacked capacitor structure 10 to prevent electrical shorting between adjacent containers 14, mask material 18′ is introduced into containers 14 to facilitate removal of HSG silicon 16 from surface 12.
While conventional spin-on processes will force some of the mask material into containers 14, trenches, or other recesses, these processes typically result in the formation of a relatively thick, but not necessarily planar layer of mask material 18′ over surface 12. Due to various factors, including the surface tension of mask material 18′ and the centrifugal forces applied to mask material 18′ during the spin-on process, mask material 18′ tends to migrate out of the small recesses (e.g., containers 14) formed in surface 12. Thus, the thickness of mask material 18′ within a container 14, trench, or other recess may not be significantly greater than the thickness of mask material 18′ covering surface 12, leaving containers 14 partially unfilled. Once the layer of material has been dispensed onto the semiconductor device structure, it is solidified or cured, such as by known photographic or soft bake processes.
In order to reduce the thickness of the layer of mask material covering the surface of the semiconductor device structure without substantially decreasing the thickness of the layer of mask material within the recesses, chemical-mechanical planarization (CMP) processes, such as chemical-mechanical polishing techniques, are typically employed. The use of CMP processes is, however, somewhat undesirable since such processes are known to create defects in the surface of the semiconductor device structure. CMP processes are also known to leave debris, or contaminants, which may be trapped in defects in the surface of the semiconductor device structure and which may subsequently cause electrical shorting of a fabricated semiconductor device. For example, if CMP processes are used to remove mask material and at least part of a conductively doped HSG silicon layer from an insulator at the surface of a stacked capacitor structure, conductive silicon particles may be trapped in defects in the surface of the insulator and subsequently cause electrical shorting between adjacent containers of the stacked capacitor. These potentially damaging contaminants may remain even when a chemical removal process, such as a wet or dry etch, follows the CMP process.
Alternatively, a photoresist may be used as the mask material. Patterning of the photoresist requires several steps in which equipment must be precisely aligned with features, such as the containers of a stacked capacitor structure, fabricated on the semiconductor substrate. Additional handling of the semiconductor device structure is also required when a photoresist is used to mask containers, trenches, or other recesses formed in a semiconductor device structure, which is somewhat undesirable.
Moreover, when conventional blanket deposition techniques are used to fill the recesses of a semiconductor device structure with a material (e.g., to fill the trenches of a shallow trench isolation structure with an electrical insulator material and to fill dual damascene trenches with a conductive material), the material typically forms a nonplanar layer over the semiconductor device structure. Such material layers typically include valleys located over recesses in the underlying semiconductor device structure and peaks located over other regions of the semiconductor device structure. Chemical-mechanical planarization is an example of a conventional technique for removing such materials from the surface of a semiconductor device structure while leaving these materials within the recesses of the semiconductor device structure. As chemical-mechanical planarization processes typically employ an abrasive pad to mechanically planarize structures, however, the peaks of the material layer may break off in larger than desired pieces and subsequently scratch the surface of the semiconductor device structure, forming defects therein.
The art does not teach a semiconductor device structure that includes a nonchemical-mechanical planarized material layer that substantially fills a container, trench, or other recess formed in the semiconductor device structure and which does not substantially cover the remainder of a surface of the semiconductor device structure or which includes only a relatively thin layer of material over the remainder of the surface. The art also fails to teach a method for forming a material layer with these features. In addition, the art lacks teaching of a method for reducing the likelihood that peaks of a nonplanar layer of material will damage a surface of a semiconductor device structure during subsequent planarization of the layer of material.